UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 908

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.12
the IICS0.STD0 bit is set to 1), communication among the master devices is performed as the number of clocks is
adjusted until the data differs. This kind of operation is called arbitration.
by which the arbitration loss occurred, and the SCL and SDA lines are both set for high impedance, which releases the
bus.
clock, when a stop condition is detected, etc.) and the ALD0 bit = 1 setting that has been made by software.
906
Transfer lines
Master 1
Master 2
When several master devices simultaneously generate a start condition (when the IICC0.STT0 bit is set to 1 before
When one of the master devices loses in arbitration, an arbitration loss flag (IICS0.ALD0 bit) is set (1) via the timing
The arbitration loss is detected based on the timing of the next interrupt request signal (INTIIC) (the eighth or ninth
For details of interrupt request timing, see 17.7 I
Arbitration
SDA
SDA
SDA
SCL
SCL
SCL
Figure 17-12. Arbitration Timing Example
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
2
C Interrupt Request Signals (INTIIC).
2
C BUS
Master 1 loses arbitration
Hi-Z
Hi-Z