UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 970

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

968
Notes 1. TCn bit is read-only.
Caution Be sure to set bits 6 to 4 to “0”. If they are set to “1”, the operation is not guaranteed.
2. INITn and STGn bits are write-only. If these bits are read, 0 is read.
(n = 0 to 3)
DCHCn
After reset:
STGn
INITn
TCn
This bit is set (1) at the last DMA transfer and cleared (0) when it is read. If DMA
transfer is executed to transfer data from the internal RAM, this bit is set (1) 4 clocks
after end of the last transfer.
• This bit is cleared (0) when DMA transfer ends. It is also cleared (0) when DMA
• If the Enn bit is set (1), do not set it until DMA transfer has been ended the
00H
MLEn
Enn
transfer is forcibly terminated by setting (1) the INITn bit.
number of times set by the DBCn register or DMA transfer is forcibly terminated
by the INITn bit.
TCn
<7>
0
1
0
1
Note 1
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
Note 2
Note 2
R/W
Setting whether DMA transfer via DMA channel n is to be enabled or disabled
Status bit that indicates whether DMA transfer via DMA channel n has ended or not
DMA transfer has not ended.
DMA transfer has ended.
DMA transfer disabled
DMA transfer enabled
When this bits is set (1) at DMA transfer end (at the terminal count
output), the Enn bit is not cleared (0) and the DMA transfer enabled state
is retained.
If the next DMA transfer start factor is input from an on-chip peripheral
I/O (hardware DMA), the DMA transfer request is acknowledged even if
the TCn bit is not read.
If the next DMA transfer start factor is input by setting the STGn bit to 1
(software DMA), the DMA transfer request is acknowledged if the TCn
bit is read and cleared (0).
When this bit is cleared (0) at DMA transfer end (at the terminal count
output), the Enn bit is cleared (0) and the DMA transfer disabled state is
entered. At the next DMA transfer request, the TCn bit
must be read and the Enn bit must be set (1).
If this bit is set (1) during DMA transfer or while DMA is suspended,
DMA transfer is forcibly terminated.
If this bit is set (1) in the DMA transfer enabled state (TCn bit = 0, Enn bit
= 1), DMA transfer is started.
6
0
Address: DCHC0 FFFFF0E0H, DCHC1 FFFFF0E2H,
User’s Manual U18279EJ3V0UD
5
0
DCHC2 FFFFF0E4H, DCHC3 FFFFF0E6H
4
0
MLEn
<3>
INITn
<2>
STGn
<1>
<0>
Enn