UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 766

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

764
(8) UARTB FIFO control register 2 (UBFIC2)
The UBFIC2 register is valid in the FIFO mode (UBFIC0.UBMOD bit = 1). It sets the timing of generating an
interrupt, using the number of transmit/receive data as a trigger. When data is transmitted, the number of
data transferred from transmit FIFO is specified as the condition of generating the interrupt. When data is
received, the number of data stored in receive FIFO is specified as the interrupt generation condition.
This register can be read or written in 16-bit units.
When the higher 8 bits of the UBFIC2 register can be used as the UBFIC2H register and the lower 8 bits, as
the UBFIC2L register, these registers can be read or written in 8-bit units.
Reset sets the UBFIC2 register to 0000H and the UBFIC2H and UBFIC2L registers to 00H.
Caution Be sure to set the UBCTL0.UBTXE bit (to disable transmission) and UBCTL0.UBRXE bit (to
UBFIC2
After reset: 0000H
disable reception) to 0 before writing data to the UBFIC2 register. If data is written to the
UBFIC2 register with the UBTXE or UBRXE bit set to 1, the operation is not guaranteed.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
•
•
•
UBTT3
15
0
Set the number of transmit FIFO transmit data to be the trigger.
Each time data of the specified number has shifted out from transmit FIFO to the
transmit shift register, the INTUBTIT signal is generated.
In the pending mode (UBFIC0.UBITM bit = 0), the INTUBTIT signal is generated
under the conditions of the pending mode.
In the pointer mode (UBFIC0.UBITM bit = 1), the number of transmit data set as
the trigger can be only 1 byte (UBTT3 to UBTT0 bits = 0000), and other settings
are prohibited. If a setting of other than 1 byte is made, the operation is not
guaranteed.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
14
0
UBTT2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
13
0
R/W
UBTT1
12
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TT3
UB
11
User’s Manual U18279EJ3V0UD
Address: FFFFFA4CH
UBTT0
TT2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
UB
10
transmit FIFO set as trigger
TT1
UB
1 byte
2 bytes
3 bytes
4 bytes
5 bytes
6 bytes
7 bytes
8 bytes
9 bytes
10 bytes
11 bytes
12 bytes
13 bytes
14 bytes
15 bytes
16 bytes
9
Number of data of
TT0
UB
8
7
0
6
0
Settable
Setting
prohibited
Pointer mode Pending mode
5
0
4
0
RT3
UB
3
RT2
UB
Settable
2
RT1
UB
1
RT0
UB
0
(1/2)