UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 749

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.2 Features
• Transfer rate: Maximum 5.33 Mbps (using a dedicated baud rate generator)
• Full-duplex communications
• Single mode and FIFO mode selectable
• Two-pin configuration
• Reception error detection function
• Interrupt sources: 5 types
• The character length of transmit/receive data is specified according to the UBCTL0 register
• Character length: 7 or 8 bits
• Parity functions: Odd, even, 0, or none
• Transmission stop bits: 1 or 2 bits
• MSB first/LSB first selectable for transfer data
• On-chip dedicated baud rate generator
• Single mode: 8-bit × 1-stage data register (UBTX register or UBRX register) is used for each of
• FIFO mode
TXDB: Transmit data output pin
RXDB: Receive data input pin
• Overflow error (FIFO mode only)
• Parity error
• Framing error
• Overrun error (single mode only)
• Reception error interrupt request signal (INTUBTIRE)
• Reception end interrupt request signal (INTUBTIR)
• Transmission enable interrupt request signal (INTUBTIT)
• FIFO transmission end interrupt request signal (INTUBTIF) (FIFO mode only)
• Reception timeout interrupt request signal (INTUBTITO) (FIFO mode only)
Transmit FIFO: UBTX register (8 bits × 16 stages).
Receive FIFO: UBRXAP register (16 bits × 16 stages)
transmission and reception.
2 bits of the higher 8 bits of the UBRXAP register are for an error flag.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
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