UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 622

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

620
(6) A/Dn conversion result registers 0 to 15 (ADnCR0 to ADnCR15), A/Dn conversion result registers 0H to
(7) A/Dn conversion result extension registers 0 to 4 (ADnECR0 to ADnECR4), A/Dn conversion result
(8) ANI00 to ANI05, ANI10 to ANI17 pins (n = 0, 1)
(9) AV
(10) AV
15H (ADnCR0H to ADnCR15H) (n = 0, 1)
The ADnCR0 to ADnCR15 and ADnCR0H to ADnCR15H registers are registers that hold the A/D conversion
results. Each time A/D conversion ends, the conversion result is loaded from the successive approximation
register (SAR) and stored in the higher 12 bits of the ADnCR0 to ADnCR15 registers. The lower 4 bits of
these registers are always 0 when read.
The higher 8 bits of the result of A/D conversion are read from the ADnCR0H to ADnCR15H registers.
To read the result of A/D conversion in 16-bit units, specify the ADnCR0 to ADnCR15 registers. To read the
higher 8 bits, specify the ADnCR0H to ADnCR15H registers.
extension registers 0H to 4H (ADnECR0H to ADnECR4H) (n = 0, 1)
The ADnECR0 to ADnECR4 and ADnECR0H to ADnECR4H registers are registers that hold the A/D
conversion results. These registers can be used only in extension buffer mode. When A/D conversion is
completed, the A/D conversion result is stored in the A/Dn conversion result extension buffer register. If
selection load trigger 1 is generated after that, the A/D conversion result is shifted from A/Dn conversion result
extension buffer registers 0 to 2 to the higher 12 bits of the ADnECR0 to ADnECR2 registers for storage. Bits
1 to 3 are always 0 when read. If selection load trigger 2 is generated, the A/D conversion result is shifted
from A/Dn conversion result extension buffer registers 3 and 4 to the higher 12 bits of the ADnECR3 and
ADnECR4 registers. Bits 1 to 3 are always 0 when read.
The higher 8 bits of the result of A/D conversion are read from the ADnECR0H to ADnECR4H registers.
To read the result of A/D conversion in 16-bit units, specify the ADnECR0 to ADnECR4 registers. To read the
higher 8 bits, specify the ADnECR0H to ADnECR4H registers.
The ANI00 to ANI05 and ANI10 to ANI17 pins are analog input pins for A/D converters 0 and 1. They input the
analog signals to be A/D converted.
Caution Make sure that the voltages input to the ANI00 to ANI05 and ANI10 to ANI17 pins do not
This pin is used for inputting the reference voltage of A/D converters 0 and 1. It converts signals input to the
analog input pin to digital signals based on the voltage applied between AV
Always make the potential at this pin the same as that at the EV
even when A/D converters 0 and 1 are not used.
The operating voltage range of the AV
4.0 to 5.5 V.
This is the ground pin of A/D converters 0 and 1. Always make the potential at this pin the same as that at the
EV
SS0
REFPn
SSn
, EV
pin (n = 0, 1)
pin (n = 0, 1)
SS1
exceed the rated values. If a voltage higher than or equal to AV
AV
conversion value of the channel is undefined, and the conversion values of the other
channels may also be affected.
, and EV
SSn
(even within the range of the absolute maximum ratings) is input to a channel, the
SS2
(V850E/IG3 only) pins even when A/D converters 0 and 1 are not used.
CHAPTER 12 A/D CONVERTERS 0 AND 1
User’s Manual U18279EJ3V0UD
REFPn
pin is EV
DD0
= EV
DD1
= EV
DD0
, EV
DD2
DD1
(V850E/IG3 only) = AV
REFPn
, and EV
REFPn
and AV
or lower than or equal to
DD2
SSn
(V850E/IG3 only) pins
(n = 0, 1).
DDn
= AV
REFPn
=