UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 755
UPD70F3453GC-8EA-A
Manufacturer Part Number
UPD70F3453GC-8EA-A
Description
MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet
1.UPD70F3451GC-UBT-A.pdf
(1191 pages)
Specifications of UPD70F3453GC-8EA-A
Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3453GC-8EA-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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UBCTL0
After reset: 10H
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
UBPWR
UBPWR
•
•
•
•
•
•
•
•
UBTXE
UBRXE
<7>
When the UBPWR bit is cleared to 0, the UARTB can be asynchronously reset.
When the UBPWR bit = 0, UARTB is in a reset state. Therefore, to operate
UARTB, the UBPWR bit must be set to 1.
When the UBPWR bit is changed from 1 to 0, all registers of UARTB are
initialized. When the UBPWR bit is set to 1 again, the UARTB registers must be
set again.
The TXDB pin output is high level when the UBPWR bit is cleared to 0.
On startup, set the UBPWR bit to 1 and then set the UBTXE bit to 1. To stop
transmission, clear the UBTXE bit to 0 and then the UBPWR bit to 0.
When the transmission unit status is to be initialized, the transmission status
may not be able to be initialized unless the UBTXE bit is set to 1 again after an
interval of two cycles of f
On startup, set the UBPWR bit to 1 and then set the UBRXE bit to 1. To stop
reception, clear the UBRXE bit to 0 and then the UBPWR bit to 0.
When the reception unit status is to be initialized, the reception status may not
be able to be initialized unless the UBRXE bit is set to 1 again after an interval
of two cycles of f
0
1
0
1
0
1
Stops supply of clocks to UARTB
Supplies clocks to UARTB
Transmission is disabled
Transmission is enabled
Reception is disabled
Reception is enabled
R/W
UBTXE
<6>
XX
Address: FFFFFA40H
User’s Manual U18279EJ3V0UD
has elapsed since the UBRXE bit was cleared to 0.
UBRXE
<5>
XX
has elapsed since the UBTXE bit was cleared to 0.
Operation clock control to UARTB
UBDIR
<4>
Transmission enable
Reception enable
UBPS1
3
UBPS0
2
UBCL
1
UBSL
0
(1/2)
753
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