UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 783

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(3) Reception interrupt request signal
(a) Reception end interrupt request signal (INTUBTIR)
• In single mode (UBFIC0.UBMOD bit = 0)
• In FIFO mode (UBFIC0.UBMOD bit = 1)
When UBCTL0.UBRXE bit = 1 and the reception of one frame of data is ended (the stop bit is detected)
in the single mode, a reception end interrupt request signal (INTUBTIR) is generated and the receive
data in the receive shift register is transferred to the UBRX register at the same time.
Also, if an overrun error occurs, the receive data at that time is not transferred to the UBRX register,
and a reception error interrupt request signal (INTUBTIRE) is generated.
If a parity error or framing error occurs during the reception operation, the reception operation
continues up to the position at which the stop bit is received.
INTUBTIRE signal occurs (the receive data in the receive shift register is transferred to the UBRX
register).
If the UBRXE bit is reset (0) during a receive operation, the receive operation is immediately stopped.
At this time, the contents of the UBRX register remain unchanged, the contents of the UARTB status
register (UBSTR) are cleared, and the INTUBTIR and INTUBTIRE signals do not occur.
No INTUBTIR signal is generated when the UBRXE bit = 0 (reception is disabled).
In the FIFO mode, the reception end interrupt request signal (INTUBTIR) occurs when data of one
frame has been received (stop bit is detected) and when as many receive data as the number specified
as the trigger by the UBFIC2.UBRT3 to UBFIC2.UBRT0 bits are transferred from the receive shift
register to receive FIFO. If an overflow error occurs, the receive data is not transferred to receive FIFO
and the reception error interrupt request signal (INTUBTIRE) occurs.
If a parity error or framing error occurs during reception, reception continues up to the reception
position of the stop bit. After reception has been completed, the INTUBTIRE signal occurs and the
receive data in the receive shift register is transferred to receive FIFO. At this time, error information is
appended as the UBRXAP.UBPEF or UBRXAP.UBFEF bit = 1. If the INTUBTIRE signal occurs, the
error data can be recognized by reading receive FIFO as a 16-bit register, UBRXAP.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD
After completion of reception, an
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