UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 278

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UPD70F3453GC-8EA-A

Manufacturer Part Number
UPD70F3453GC-8EA-A
Description
MCU 32BIT 128KB FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
V850E/Ix3r
Datasheet

Specifications of UPD70F3453GC-8EA-A

Core Processor
RISC
Core Size
32-Bit
Speed
64MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
56
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3.5 V ~ 5.5 V
Data Converters
A/D 10x12b, 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3453GC-8EA-A
Manufacturer:
Renesas Electronics America
Quantity:
10 000
276
TAAmIOC2
TAAnOPT0
(e) TAAm I/O control register 2 (TAAmIOC2)
(f) TAAn option register 0 (TAAnOPT0)
(g) TAAn counter read buffer register (TAAnCNT)
(h) TAAn capture/compare registers 0 and 1 (TAAnCCR0 and TAAnCCR1)
Note Set the valid edge selection of the unused alternate external input signals to “No edge detection”.
The value of the 16-bit counter can be read by reading the TAAnCNT register.
These registers function as capture registers or compare registers depending on the setting of the
TAAmOPT0.TAAmCCSa bit.
When the registers function as capture registers, they store the count value of the 16-bit counter when
the valid edge input to the TIAma pin is detected.
When the registers function as compare registers and when D
INTTAnCCa signal is generated when the counter reaches (D
TOAm0 and TOAm1 pins are inverted.
Remark
0
0
V850E/IF3: n = 0 to 4, m = 2, 4, a = 0, 1
V850E/IG3: n = 0 to 4, m = 2 to 4, a = 0, 1
Figure 6-39. Register Setting in Free-Running Timer Mode (2/2)
0
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
TAAmCCS1
0/1
0
TAAmCCS0
User’s Manual U18279EJ3V0UD
0/1
0
TAAmEES1
0/1
0
TAAmEES0 TAAmETS1 TAAmETS0
0/1
0
a
0
0
a
is set to the TAAnCCRa register, the
+ 1), and the output signals of the
TAAnOVF
0/1
0
Select valid edge of
external event count
input (TIAm0 pin)
Overflow flag
Specifies if TAAmCCR0
register functions as
capture or compare register
0: Compare register
1: Capture register
Specifies if TAAmCCR1
register functions as
capture or compare register
0: Compare register
1: Capture register
Note

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