UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 949

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Bus clock division control register (DVC)
The DVC register is used to specify insertion of an idle state (TI) after completion of a write cycle, and an
external bus clock frequency.
This register can be read or written in 8-bit units.
Reset sets this register to 81H.
Cautions 1. The internal ROM, internal RAM, and on-chip peripheral I/O areas are not subject to idle
Note Can be set only when f
Cautions 1. Be sure to set the CLKOUT pin in the port mode before changing the setting of the
Setting prohibited when 32 MHz < f
After reset: 81H
DVC
2. Write to the DVC register after reset once (initial setting), and then do not change the set
2. Set the external bus clock frequency (f
3. Be sure to set bits 2 to 6 to “0”. If they are set to “1”, the operation is not guaranteed.
state insertion.
value. Also, do not access an external memory area until the initial setting of the DVC
register is complete.
However, it is possible to access external memory areas whose initialization settings
are complete.
DVC1 and DVC0 bits. Changing the setting of the DVC1 and DVC0 bits while the
alternate function (CLKOUT) is used is prohibited.
BCWI
DVC1
BCWI
0
1
0
0
1
1
R/W
Not inserted
Inserted (only when BCC.BCn1 bit = 1)
DVC0
0
CHAPTER 18 BUS CONTROL FUNCTION
0
1
0
1
CLK
Address: FFFFF48EH
≤ 32 MHz.
Specification of idle state inserted after write cycle ends
f
f
Setting prohibited
f
CLK
CLK
CLK
User’s Manual U18279EJ3V0UD
0
/1
/2
/4
Note
Specification of external bus clock frequency (f
CLK
≤ 64 MHz
0
BUS
0
) in a range of 16 MHz ≤ f
0
DVC1
BUS
DVC0
)
BUS
≤ 32 MHz.
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