UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 754

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.4 Control Registers
752
(1) UARTB control register 0 (UBCTL0)
The UBCTL0 register controls the transfer operations of UARTB.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 10H.
Cautions 1. When using UARTB, set the external pins related to the UARTB function in the alternate-
Remark
2. Be sure to input a high level to the RXDB pin when setting the external pins related to
When reception is disabled, the receive shift register does not detect a start bit. No shift-in
processing or transfer processing to the receive data register is performed, and the contents of the
receive data register are retained.
When reception is enabled, the receive shift operation starts, in synchronization with the detection
of the start bit, and when the reception of one frame is completed, the contents of the receive shift
register are transferred to the receive data register.
A reception end interrupt request signal (INTUBTIR) is also generated, in synchronization with the
transfer to the receive data register (in FIFO mode, transfer triggered by reaching set number of
receive data).
If data is stored in receive FIFO when the next data does not come (start bit is not detected) after
the next data reception wait time specified by the UBFIC1.UBTC4 to UBFIC1.UBTC0 bits has
elapsed in the FIFO mode, a reception timeout interrupt request signal (INTUBTITO) is generated.
function mode, set UARTB control register 2 (UBCTL2). Then set the UBPWR bit to 1
before setting the other bits.
the UARTB function in the alternate-function mode. If a low level is input, it is judged
that a falling edge is input after the UBRXE bit has been set to 1, and reception may be
started.
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE B (UARTB)
User’s Manual U18279EJ3V0UD