UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 426

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

424
Table 8-4. Function of Capture/Compare Register in Each Mode and How to Write Compare Register
Interval timer
External event counter
External trigger pulse output
One-shot pulse output
PWM output
Free-running timer
Pulse width measurement
Triangular-wave WPM output
Encoder compare
(a) Function as compare register
(b) Function as capture register
The following table shows the functions of the capture/compare register in each mode, and how to write data to
the compare register.
Notes 1. In the V850E/IF3, this mode can be set only in TMT1.
Remark
The TTnCCR0 register can be rewritten even when the TTnCTL0.TTnCE bit = 1.
The set value of the TTnCCR0 register is transferred to the CCR0 buffer register. When the value of the
16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal
(INTTTEQCn0) is generated. If TOTm0 pin output is enabled at this time, the output of the TOTm0 pin is
inverted.
When the TTnCCR0 register is used as a cycle register in the interval timer mode, or when the TTmCCR0
register is used as a cycle register in the external event count mode, external trigger pulse output mode,
one-shot pulse output mode, PWM output mode, triangular-wave PWM output mode, or encoder compare
mode, the value of the 16-bit counter is cleared (0000H) if its count value matches the value of the CCR0
buffer register.
The compare register is not cleared by setting the TTnCTL0.TTnCE bit to 0.
When the TTmCCR0 register is used as a capture register in the free-running timer mode (when the
TTmCCR0 register is used as a capture register), the count value of the 16-bit counter is stored in the
TTmCCR0 register if the valid edge of the capture trigger input pin (TITm0 pin) is detected. In the pulse-
width measurement mode, the count value of the 16-bit counter is stored in the TTmCCR0 register and the
16-bit counter is cleared (0000H) if the valid edge of the capture trigger input pin (TITm0 pin) is detected.
Even if the capture operation and reading the TTmCCR0 register conflict, the correct value of the
TTmCCR0 register can be read.
The capture register is cleared by setting the TTmCTL0.TTmCE bit to 0.
Remark
2. Writing to the TTnCCR1 register is the trigger.
Operation Mode
Note 1
For anytime write and batch write, see 8.6 (2) Anytime write and batch write.
Note 1
V850E/IF3: m = 1
V850E/IG3: m = 0, 1
Note 1
Note 1
Note 1
Note 1
Note 1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
Compare register
Compare register
Compare register
Compare register
Compare register
Capture/compare register
Capture register
Compare register
Compare register
User’s Manual U18279EJ3V0UD
TTnCCR0 Register
Anytime write
Anytime write
Batch write
Anytime write
Batch write
Anytime write
None
Batch write
Anytime write
How to Write Compare Register
Note 2
Note 2
Note 2