UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 216

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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(1) Counter basic operation
This section explains the basic operation of the 16-bit counter. For details, refer to the description of the
operation in each mode.
Remark
(a) Counter start operation
(b) Clear operation
(c) Overflow operation
(d) Counter read operation during counting operation
• In external event count mode
• In modes other than the above
The 16-bit counter is cleared to 0000H when its value matches the value of the compare register and is
cleared, and when its value is captured and cleared. The counting operation from FFFFH to 0000H that
takes place immediately after the counter has started counting or when the counter overflows is not a
clearing operation. Therefore, the INTTAnCC0 and INTTAnCC1 interrupt signals are not generated.
The 16-bit counter overflows when the counter counts up from FFFFH to 0000H in the free-running mode
or pulse width measurement mode. If the counter overflows, the TAAnOPT0.TAAnOVF bit is set to 1 and
an interrupt request signal (INTTAnOV) is generated. Note that the INTTAnOV signal is not generated
under the following conditions.
• Immediately after a counting operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured and cleared in the pulse width measurement mode and the counter counts up
Caution After the overflow interrupt request signal (INTTAnOV) has been generated, be sure to
The value of the 16-bit counter of TAAn can be read by using the TAAnCNT register during the count
operation. When the TAAnCTL0.TAAnCE bit = 1, the value of the 16-bit counter can be read by reading
the TAAnCNT register. When the TAAnCTL0.TAAnCE bit = 0, the 16-bit counter is FFFFH and the
TAAnCNT register is 0000H.
from FFFFH to 0000H
When the TAAmCTL0.TAAmCE bit is set from 0 to 1, the 16-bit counter is set to 0000H.
After that, it counts up to 0001H, 0002H, 0003H, … each time the valid edge of external event count
input (TIAm0) is detected.
Starts counting from the default value FFFFH.
It counts up from FFFFH to 0000H, 0001H, 0002H, 0003H, and so on.
V850E/IF3: n = 0 to 4, m = 2, 4
V850E/IG3: n = 0 to 4, m = 2 to 4
check that the overflow flag (TAAnOVF bit) is set to 1.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER AA (TAA)
User’s Manual U18279EJ3V0UD