UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 678

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

676
(1) Error detection function
Cautions 1. Selection trigger 1, selection trigger 2, selection load trigger 1, and selection load trigger
(a) Error detection by generation of selection trigger 1 or 2 during A/D conversion
The extension buffer mode has an error detection function. If a trigger (selection trigger 1, selection trigger 2,
selection load trigger 1, or selection load trigger 2) is generated during A/D conversion, an error occurs. The
error is detected by the ADnFLG.ADnTERR2 and ADnFLG.ADnTERR1 flags, and ADnFLGB.ADnTERRB2
and ADnFLGB.ADnTERRB1 flags.
Selection load trigger 1
Selection load trigger 2
If selection trigger 1 is generated during A/D conversion, the ADnFLGB.ADnTERRB1 flag is set to 1 and
A/D conversion by selection trigger 1 is ignored. If selection load trigger 1 is generated next, the value of
the ADnTERRB1 flag is stored in the ADnFLG.ADnTERR1 flag.
Similarly, if selection trigger 2 is generated during A/D conversion, the ADnFLGB.ADnTERRB2 flag is set
to 1 and A/D conversion by selection trigger 2 is ignored. When selection load trigger 2 is generated next,
the value of the ADnTERRB2 flag is stored in the ADnFLG.ADnTERR2 flag.
Selection trigger 1
Selection trigger 2
2. Selection trigger 1 or 2 is ignored, even if it is generated again, during a period of up to
TERRB1 flag
TERRB2 flag
ADnCS flag
TERR1 flag
TERR2 flag
2 are generated when asynchronous signals ITRG1 to ITRG4, LDTRG1, and LDTRG2
signals are synchronized. Although the timing of inputting these triggers seems to be the
same, their simultaneous operation is not guaranteed because the asynchronous signals
are synchronized.
2.5 basic clocks (f
CHAPTER 12 A/D CONVERTERS 0 AND 1
AD01
) after the trigger is once generated (no error occurs).
User’s Manual U18279EJ3V0UD