UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 646

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

644
(15) A/D trigger rising edge, falling edge specification registers (ADTR, ADTF)
Caution When not using these pins as the ADTRGn/INTADTn pins, be sure to set the ADTFn and ADTRn
Remark
Remark
ADTFn
0
0
1
1
The ADTR and ADTF registers are registers that specify the trigger mode of the ADTRG0/INTADT0 and
ADTRG1/INTADT1 pins and can specify the valid edge independently for each pin (rising edge, falling edge, or
both rising and falling edges).
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external trigger input of the A/D converter n (alternate
Table 12-8. Valid Edge Specification of ADTRG0/INTADT0 and ADTRG1/INTADT1 Pins
bits to 00.
n = 0, 1
For the valid edge specification, see Table 12-8.
ADTR
ADTF
After reset: 00H
After reset: 00H
function)/external interrupt function (alternate function) to the port mode, an edge may be
detected. Therefore, be sure to set the ADTFn and ADTRn bits to 00, and then set the port
mode.
ADTRn
0
1
0
1
0
0
No edge detected
Rising edge
Falling edge
Both rising and falling edges
R/W
R/W
CHAPTER 12 A/D CONVERTERS 0 AND 1
0
0
Address: FFFFF2F2H
Address: FFFFF2F0H
User’s Manual U18279EJ3V0UD
0
0
0
0
Valid Edge Specification
0
0
0
0
ADTR1
ADTF1
ADTR0
ADTF0