UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 815

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1. These bits can only be rewritten when the CBnPWR bit = 0. However, the CBnPWR bit can be
2. If the CBnSCE bit is read while it is 1, the next communication operation is started.
3. The CBnSCE bit is not set to 0 one communication clock before the end of the last data
4. To start the reception, a dummy read is necessary.
set to 1 at the same time as these bits are rewritten.
reception, the next communication operation is automatically started.
To start communication operation again after reading the last data, set the CBnSCE bit to 1 and
perform a dummy read of the CBnRX register.
CBnTMS
CBnDIR
• When using single transmission or transmission/reception mode with
• When using DMA, use the continuous transfer mode.
CBnSCE
• In master mode
• In slave mode
• In single transmission or transmission/reception mode, or continuous transmission
This bit enables or disables the communication start trigger.
(a) In single reception mode
(b) In continuous reception mode
This bit enables or disables the communication start trigger.
(a) In single reception mode or continuous reception mode
or transmission/reception mode
The function of the CBnSCE bit is invalid. It is recommended to set this bit to 1.
communication type 2 or 4 (CBnCTL1.CBnDAP bit = 1), write the transfer data to
the CBnTX register after checking that the CBnSTR.CBnTSF bit is 0.
0
1
0
1
0
1
Set the CBnSCE bit to 0 before reading the receive data (CBnRX register)
Set the CBnSCE bit to 0 one communication clock before reception of the last
data is ended
Set the CBnSCE bit to 1
Note 1
Note 1
Single transfer mode
Continuous transfer mode
Communication start trigger invalid
Communication start trigger valid
MSB first
LSB first
CHAPTER 16 CLOCKED SERIAL INTERFACE B (CSIB)
Note 3
Specification of transfer direction mode (MSB/LSB)
.
Specification of start transfer disable/enable
User’s Manual U18279EJ3V0UD
Note 4
Transfer mode specification
.
Note 2
.
(2/2)
813