UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 628

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

626
(3) A/D converter n conversion channel specification register (ADnCHEN)
Remark
Cautions 1. The A/D conversion operation is prohibited when the ADnCHEN register = 0000H.
The ADnCHEN register is a register that specifies the analog input pin, number of conversion times, and
conversion result register.
This register is used to specify an analog input pin in the A/D trigger mode, A/D trigger polling mode, and
hardware trigger mode. The ADnCRm register corresponds to an analog input pin on a one-to-one basis. Use
the bits (AD0CHEN00 to AD0CHEN05 and AD1CHEN00 to AD1CHEN07) corresponding to the ANI00 to
ANI05 and ANI10 to ANI17 pins. If two or more analog input pins are specified, they are sequentially selected,
starting from the one with the lowest number, for conversion (when AD1CHEN register = 004DH: ANI10 →
ANI12 → ANI13 → ANI16). If an analog input pin that is not specified is skipped during successive conversion.
In the conversion channel specification mode, specify the number of times of conversion and a conversion
result register. Specify an analog input pin by using the ADnCH1 register. A value set to the lower bits of the
ADnCHEN register, justified to the lowest bit, is the number of times of conversion. These bits correspond to
the ADnCRm and ADnCHmH registers on a one-to-one basis.
Because the ADnCHEN register is of master/slave configuration, a new analog input pin can be set to the
master register during A/D conversion operation. The set value of the master register is transferred to a slave
register after completion of A/D conversion (after the A/Dn conversion end interrupt request signal (INTADn) is
generated).
This register can be read or written in 16-bit units.
When the higher 8 bits of the ADnCHEN register are used as the ADnCHENH register and the lower 8 bits, as
the ADnCHENL register, these registers can be read or written in 1-bit or 8-bit units.
Reset sets this register to 0000H.
2. Do not write the ADnCHEN register when the ADnSCM.ADnPS bit = 0. If it is written, the
3. To change the setting of the ADnCHEN register when the ADnSCM.ADnCE bit = 1 in the
See Table 12-3 Specifying Analog Input Pin in A/D Trigger Mode, A/D Trigger Polling Mode,
and Hardware Trigger Mode for how to specify an analog input pin in the A/D trigger mode, A/D
trigger polling mode, and hardware trigger mode.
conversion and the A/D conversion result register in the conversion channel specification mode, see
Table 12-4 Correspondence Among Set Value of ADnCHEN Register, Number of Times of
Conversion, and A/D Conversion Result Register in Conversion Channel Specification Mode.
ADnCHEN
(n = 0, 1)
If the ADnCHEN register = 0000H, the operation is the same as when the ADnCHEN
register = 0001H.
CPU deadlocks.
hardware trigger mode, be sure to set the ADnCE bit to 0.
After reset: 0000H
CHEN
ADn
15
CHEN
ADn
14
CHEN
ADn
CHAPTER 12 A/D CONVERTERS 0 AND 1
R/W
13
CHEN
ADn
12
Address: AD0CHEN FFFFF224H, AD1CHEN FFFFF2A4H
User’s Manual U18279EJ3V0UD
CHEN
ADn
11
CHEN
ADn
10
CHEN
ADn
9
CHEN
ADn
8
CHEN
ADn
7
For how to specify the number of times of
CHEN
ADn
6
CHEN
ADn
5
CHEN
ADn
4
CHEN
ADn
3
CHEN
ADn
2
CHEN
ADn
1
CHEN
ADn
0