UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 433

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(d) Count value holding operation
(e) Counter read operation during count operation
(f) Underflow operation
(g) Interrupt operation
Caution After the overflow interrupt request signal (INTTTIOVn) has been generated, be sure to
The value of the 16-bit counter is held by the TTmCTL2.TTmECC bit in the encoder compare mode. The
value of the 16-bit counter is reset to FFFFH when the TTmECC bit = 0 and TTmCTL0.TTmCE bit = 0.
When the TTmCE bit is set to 1 next time, the set value of the TTmTCW register is transferred to the 16-bit
counter and the counter continues its count operation.
If the TTmECC bit = 1 and TTmCE bit = 0, the value of the 16-bit counter is held. When the TTmCE bit is
set to 1 next time, the counter resumes the count operation from the held value.
The value of the 16-bit counter of TMTn can be read by using the TTnCNT register during the count
operation. When the TTnCTL0.TTnCE bit = 1, the value of the 16-bit counter can be read by reading the
TTnCNT register. If the TTmCNT register is read when the TTmCTL2.TTmECC bit = 0 and TTmCE bit = 0,
however, it is 0000H. The held value of the TTmCNT register is read if the register is read when the
TTmECC bit = 1 and TTmCE bit = 0.
The 16-bit counter underflow occurs at the timing when the 16-bit counter value changes from 0000H to
FFFFH in the encoder compare mode. When underflow occurs, the TTmOPT1.TTmEUF bit is set to 1 and
an interrupt request signal (INTTTIOVm) is generated.
TMTn generates the following four types of interrupt request signals.
• INTTTEQCn0 interrupt: This signal functions as a match interrupt request signal of the CCR0 buffer
• INTTTEQCn1 interrupt: This signal functions as a match interrupt request signal of the CCR1 buffer
• INTTTIOVn interrupt:
• INTTIECm interrupt:
check that the overflow flag (TTnOVF, TTmEOF bits) is set to 1.
CHAPTER 8 16-BIT TIMER/EVENT COUNTER T (TMT)
This signal functions as a valid edge detection interrupt request signal of the
register and as a capture interrupt request signal to the TTnCCR0 register.
register and as a capture interrupt request signal to the TTnCCR1 register.
This signal functions as an overflow interrupt request signal.
encoder clear input (TECRm pin).
User’s Manual U18279EJ3V0UD
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