UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 348

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from
the TOBnb pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and
restarted. (The output of the TOBn0 pin is inverted. The TOBnb pin outputs a high-level regardless of the status
(high/low) when a trigger occurs.)
count value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H. The compare
match interrupt request signal INTTBnCCb is generated when the count value of the 16-bit counter matches the value
of the CCRb buffer register.
bit counter matches the value of the CCR0 buffer register and the 16-bit counter is cleared to 0000H.
to 1 is used as the trigger.
346
TABnCTL0
16-bit timer/event counter AB waits for a trigger when the TABnCE bit is set to 1. When the trigger is generated, the
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal INTTBnCC0 is generated when the 16-bit counter counts next time after its
The value set to the TABnCCRa register is transferred to the CCRa buffer register when the count value of the 16-
The valid edge of an external trigger input signal (TRGBn), or setting the software trigger (TABnCTL1.TABnEST bit)
Remark
Active level width = (Set value of TABnCCRb register) × Count clock cycle
Cycle = (Set value of TABnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TABnCCRb register)/(Set value of TABnCCR0 register + 1)
(a) TABn control register 0 (TABnCTL0)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
n = 0, 1
a = 0 to 3
b = 1 to 3
TABnCE
0/1
Figure 7-22. Setting of Registers in External Trigger Pulse Output Mode (1/3)
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
User’s Manual U18279EJ3V0UD
0
0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
0/1
0/1
Select count clock
0: Stop counting
1: Enable counting
Note