UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 969

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
n (n = 0 to 3).
The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel
These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only.)
Reset sets these registers to 00H.
Cautions 1. If transfer has been ended with the MLEn bit set to 1 and if the next transfer request is made
2. Set the MLEn bit when the target channel is in one of the following periods (the operation is
3. If DMA transfer is forcibly terminated in the last transfer cycle with the MLEn bit set to 1, the
4. Upon end of DMA transfer (during terminal count), each bit is updated with the Enn bit cleared
5. Be sure to read (clear to 0) the TCn bit after end of DMA transfer (after terminal count). The
6. Do not set the Enn and STGn bits while DMA is suspended. Otherwise, the operation is not
7. Do not end DMA transfer by clearing the Enn bit to 0.
8. The relationship between the status of DMA transfer and the register value is as follows.
by DMA transfer (hardware DMA) that is started by an interrupt from an on-chip peripheral I/O,
the next transfer is executed with the TCn bit set to 1 (not automatically cleared to 0).
not guaranteed if the bit is set at any other time).
• Period from system reset to the generation of the first DMA transfer request
• Period from end of DMA transfer (after terminal count) to the generation of the next DMA
• Period from forced termination of DMA transfer (after the INITn bit was set to 1) to the
operation is performed in the same manner as when transfer is ended (the TCn bit is set to 1).
(The Enn bit is cleared to 0 upon forced termination, regardless of the value of the MLEn bit.)
In this case, the Enn bit must be set to 1 and the TCn bit must be read (cleared to 0) when the
next DMA transfer request is made.
to 0 and then the TCn bit set to 1. If the statuses of the TCn bit and Enn bit are polled and if
the DCHCn register is read while each bit is updated, therefore, a value indicating the status
“transfer not ended and prohibited” (TCn bit = 0 and Enn bit = 0) may be read (this is not
abnormal).
TCn bit does not have to be read (cleared to 0) only if the following two conditions are
satisfied.
• The MLEn bit is set to 1 upon end of DMA transfer (during terminal count).
• The next DMA transfer (hardware DMA) start factor is an interrupt from the on-chip
If even one of these conditions is not satisfied, be sure to read (clear to 0) the TCn bit before
the next DMA transfer request is generated.
The operation cannot be guaranteed if the next DMA transfer request is generated while the
TCn bit is set to 1.
guaranteed.
• DMA transfer is in progress:
• DMA transfer is aborted:
• DMA transfer is stopped (ends): TCn bit = 1
transfer request
generation of the next DMA transfer request
peripheral I/O (hardware DMA)
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
User’s Manual U18279EJ3V0UD
TCn bit = 0, Enn bit = 1
TCn bit = 0, Enn bit = 0
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