UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 336

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

counts each time the valid edge of external event count input is detected. Additionally, the set value of the TABnCCR0
register is transferred to the CCR0 buffer register.
cleared to 0000H, and a compare match interrupt request signal (INTTBnCC0) is generated.
set to TABnCCR0 register + 1” times.
334
TABnIOC2
When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is
The INTTBnCC0 signal is generated each time the valid edge of the external event count has been detected “value
TABnCTL0
TABnCTL1
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
(c) TABn I/O control register 2 (TABnIOC2)
(d) TABn counter read buffer register (TABnCNT)
(e) TABn capture/compare register 0 (TABnCCR0)
The count value of the 16-bit counter can be read by reading the TABnCNT register.
If the TABnCCR0 register is set to D
generated when the number of external events has reached (D
TABnCE
Figure 7-15. Register Setting for Operation in External Event Count Mode (1/2)
0
0/1
0
TABnEST
0
0
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABnEEE
0
0
0
User’s Manual U18279EJ3V0UD
0
0
0
0
, the compare match interrupt request signal (INTTBnCC0) is
TABnEES1
0/1
0
0
TABnEES0
TABnCKS2 TABnCKS1 TABnCKS0
TABnMD2 TABnMD1 TABnMD0
0/1
0
0
TABnETS1
0
0
+ 1).
0
0
TABnETS0
0
0
1
Select valid edge
of external event
count input (EVTBn pin)
0: Stop counting
1: Enable counting
0, 0, 1:
External event count mode