UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 906

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.8 Interrupt Request Signal (INTIIC) Generation Timing and Wait Control
corresponding wait control, as shown below.
904
The setting of the IICC0.WTIM0 bit determines the timing by which the INTIIC signal is generated and the
Notes 1.
Remark The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
(5) Stop condition detection
WTIM0 Bit
• Slave device operation:
• Master device operation:
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
The four wait cancellation methods are as follows.
• By writing data to the IIC0 register
• By setting the IICC0.WREL0 bit (canceling wait state)
• By setting the IICC0.STT0 bit (generating start condition)
• By setting the IICC0.SPT0 bit (generating stop condition)
Note Master only
When an 8-clock wait has been selected (WTIM0 bit = 0), whether or not ACK has been generated must be
determined prior to wait cancellation.
The INTIIC signal is generated when a stop condition is detected.
0
1
2.
wait control are both synchronized with the falling edge of these clock signals.
The slave device’s INTIIC signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the SVA0 register.
At this point, ACK is generated regardless of the value set to the IICC0.ACKE0 bit. For a slave device
that has received an extension code, the INTIIC signal occurs at the falling edge of the eighth clock.
When the address does not match after restart, the INTIIC signal is generated at the falling edge of the
ninth clock, but no wait occurs.
If the received address does not match the contents of the SVA0 register and extension codes have not
been received, neither the INTIIC signal nor a wait occurs.
Address
9
9
Notes 1, 2
Notes 1, 2
Table 17-3. INTIIC Signal Generation Timing and Wait Control
During Slave Device Operation
Data Reception
Interrupt and wait timing are determined depending on the conditions in Notes 1
and 2 above regardless of the WTIM0 bit.
Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
the WTIM0 bit.
8
9
Note 2
Note 2
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
Data Transmission
8
9
Note 2
Note 2
2
C BUS
Note
Note
Address
9
9
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9