UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 175

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.7.2
of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit.
P21 to P27
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
<Example>
Port 2 latch
0
Cautions on bit manipulation instruction for port n register (Pn)
P20
0
0
When P20 pin is an output port, P21 to P27 pins are input ports (all pin statuses are high level), and
the value of the port latch is 00H, if the output of P20 pin is changed from low level to high level via
a bit manipulation instruction, the value of the port latch is FFH.
Explanation: The target bits of writing to and reading from the Pn register of a port whose PMnm bit
is 1 are in the output latch status and pin status, respectively.
A bit manipulation instruction is executed in the following order in the V850E/IF3 and V850E/IG3.
<1> The Pn register is read in 8-bit units.
<2> The targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the value of the output latch (0) of P20 pin, which is an output port, is read, while the
pin statuses of P21 to P27 pins, which are input ports, are read. If the pin statuses of P21 to P27
pins are high level at this time, the read value is FEH.
The value is changed to FFH by the manipulation in <2>.
FFH is written to the output latch by the manipulation in <3>.
0
Pin status: High level
Bit manipulation instruction for P20 bit
<1> P2 register is read in 8-bit units.
<2> Set (1) the P20 bit.
<3> Write the results of <2> to the output latch of P2 register in 8-bit units.
Low-level output
0
• In the case of P20, an output port, the value of the port latch (0) is read.
• In the case of P21 to P27, input ports, the pin status (1) is read.
Figure 4-5. Bit Manipulation Instruction (P20 Pin)
0
0
CHAPTER 4 PORT FUNCTIONS
0
User’s Manual U18279EJ3V0UD
Bit manipulation
instruction
(set1 0, P2[r0])
is executed for
P20 bit.
P21 to P27
Port 2 latch
1
P20
1
1
1
Pin status: High level
High-level output
1
1
1
1
173