UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 587

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<1> Matching of the count value of the 16-bit counter and the value of the TABnCCRm register as a result of
<2> Even if the PWM output does not change, the interrupt generated upon a match between the 16-bit
<3> The next match between the 16-bit counter and TABnCCRm register is valid after the counter has changed
If the TABnCCRm register is rewritten after its value matches the value of the 16-bit counter, the next match is
ignored after the first match occurs and the rewritten value is not reflected to the TOBnTm pin output. If the
register is rewritten while the counter is counting down, the match that occurs after the counter starts counting
down is valid (the match that occurs after the counter has started counting up is valid if the register is rewritten
while the counter is counting up).
Remarks 1. i, r, k = Set value of TABnCCRm register
Figure 10-25. Example of Rewriting TABnCCR1 to TABnCCR3 Registers (Rewriting After Match Occurs)
(c) Rewriting TABnOPT1 register
rewriting the register is ignored after a match signal has been generated, and the PWM output does not
change.
counter value and the TABnCCRm register value (INTTBnCCm) is output.
its counting direction to up or down, and the PWM output changes.
The interrupt culling counter is cleared when the TABnOPT1 register is written. When the interrupt culling
counter has been cleared, the measured number of times the interrupt has occurred is discarded.
Consequently, the interrupt generation interval is temporarily extended.
To avoid this operation, rewrite the TABnOPT1 register in the intermittent batch rewriting mode (transfer
culling mode).
For details of rewriting the TABnOPT1 register, see 10.4.3 Interrupt culling function.
2. n = 0, 1, m = 1 to 3
CCRm buffer
INTTBnCCm
TABnCCRm
pin output
TOBnTm
counter
register
register
signal
16-bit
CHAPTER 10 MOTOR CONTROL FUNCTION
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