UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 1031

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21.3 HALT Mode
21.3.1 Setting and operation status
operating. Clock supply to the other on-chip peripheral functions continues.
set. The on-chip peripheral functions that are independent of instruction processing by the CPU continue operating.
normal operation mode for intermittent operation.
21.3.2 Releasing HALT mode
interrupt request signal, and a reset signal (RESET pin input, reset signal (WDTRES) generation by watchdog timer
overflow, reset signal (LVIRES) generation by low-voltage detector (LVI), or reset signal (POCRES) generation by
power-on-clear circuit (POC)).
Non-maskable interrupt request signal
Unmasked maskable interrupt request
signal
The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode.
When HALT mode is set, clock supply is stopped to the CPU only. The clock generator and PLL continue
As a result, program execution is stopped, and the internal RAM retains the contents before the HALT mode was
Table 21-3 shows the operation status in the HALT mode.
The average power consumption of the system can be reduced by using the HALT mode in combination with the
Cautions 1. Insert five or more NOP instructions after the HALT instruction.
The HALT mode is released by a non-maskable interrupt request signal (INTWDT), an unmasked maskable
After the HALT mode has been released, the normal operation mode is restored.
(1) Releasing HALT mode by non-maskable interrupt request signal or unmasked maskable interrupt
request signal
The HALT mode is released by a non-maskable interrupt request signal (INTWDT) or an unmasked maskable
interrupt request signal, regardless of the priority of the interrupt request. If the HALT mode is set in an
interrupt servicing routine, however, an interrupt request that is issued later is serviced as follows.
(a) If an interrupt request signal with a priority lower than or same as the interrupt currently being serviced is
(b) If an interrupt request signal with a priority higher than that of the interrupt currently being serviced is
generated, the HALT mode is released, but the newly generated interrupt request signal is not
acknowledged. The interrupt request signal itself is retained. Therefore, execution starts at the next
instruction after the HALT instruction.
issued (including a non-maskable interrupt request signal), the HALT mode is released and that interrupt
request signal is acknowledged. Therefore, execution branches to the handler address.
Release Source
2. If the HALT instruction is executed while an interrupt request is being held pending, the HALT
mode is set but is released immediately by the pending interrupt request.
Table 21-2. Operation After Releasing HALT Mode by Interrupt Request Signal
Execution branches to the handler address
Execution branches to the handler
address or the next instruction is
executed
CHAPTER 21 STANDBY FUNCTION
Interrupt Enabled (EI) Status
User’s Manual U18279EJ3V0UD
The next instruction is executed
Interrupt Disabled (DI) Status
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