UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 1036

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

1034
Unmasked maskable interrupt request
Item
Clock generator, PLL
System clock (f
CPU
External bus interface
DMA
Interrupt controller
Timer
Watchdog timer
Serial interface
A/D converters 0 to 2
Clock monitor
Low-voltage detector
Power-on-clear circuit
Port function
Internal data
(2) Releasing STOP mode by RESET pin input or by LVIRES or POCRES signal generation
Note
The same operation as the normal reset operation is performed.
μ
PD70F3454GC-8EA-A and 70F3454F1-DA9-A only
Release Source
XX
)
Table 21-6. Operation After Releasing STOP Mode by Interrupt Request Signal
Setting of STOP Mode
TAA0 to TAA4
TAB0, TAB1
TMT0, TMT1
TMM0 to TMM3
CSIB0 to CSIB2
UARTA0 to UARTA2
UARTB
I
2
C
Note
Table 21-7. Operation Status in STOP Mode
Stops operation
Stops supply
Stops operation
See Table 2-2 Pin Operation Status in Operation Modes.
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Operable when SCKBn input clock is selected as count clock (in slave mode) (n = 0 to
2)
Stops operation
Stops operation
Stops operation
Stops operation
Stops operation
Operable
Operable
Retains status before STOP mode was set.
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the STOP mode was set.
Execution branches to the handler
address or the next instruction is
executed after securing oscillation
stabilization time
CHAPTER 21 STANDBY FUNCTION
Interrupt Enabled (EI) Status
User’s Manual U18279EJ3V0UD
Operation Status
The next instruction is executed after
securing oscillation stabilization time
Interrupt Disabled (DI) Status