UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 361

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOBnb pin.
After the one-shot pulse is output, the 16-bit counter is set to 0000H, stops counting, and waits for a trigger. When the
trigger is generated again, the 16-bit counter starts counting from 0000H. If a trigger is generated again while the
one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTBnCCb
is generated when the count value of the 16-bit counter matches the value of the CCRb buffer register.
used as the trigger.
TABnCTL1
TABnCTL0
When the TABnCE bit is set to 1, 16-bit timer/event counter AB waits for a trigger. When the trigger is generated,
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTBnCC0 is generated when the 16-bit counter counts after its
The valid edge of an external trigger input (TRGBn) or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is
Remark
Output delay period = (Set value of TABnCCRb register) × Count clock cycle
Active level width = (Set value of TABnCCR0 register − Set value of TABnCCRb register + 1) × Count clock cycle
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
n = 0, 1, b = 1 to 3
TABnCE
0/1
0
Figure 7-26. Setting of Registers in One-Shot Pulse Output Mode (1/3)
TABnEST
0/1
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AB (TAB)
TABnEEE
0/1
0
User’s Manual U18279EJ3V0UD
0
0
0
0
TABnMD2 TABnMD1 TABnMD0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
0
0/1
1
0/1
1
0, 1, 1:
One-shot pulse output mode
0: Operate on count clock
1: Count external event
Generate software trigger
when 1 is written
Select count clock
0: Stop counting
1: Enable counting
selected by TABnCKS0 to
TABnCKS2 bits
input signal
Note
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