UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 171

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(1) Digital noise elimination 0 control register n (INTNFCn)
Note When using the INTPn pin, be sure to set the INTNFENn bit to 1 (digital noise elimination enabled).
The INTNFCn register is used to select the sampling clock that is used to eliminate digital noise on the INTPn
pin. If the same level is not detected on this pin three times in sequence using the clock selected by the
INTNFCn register, the signal is eliminated as noise.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Cautions 1. If the input signal lasts for the duration of 2 or 3 clocks, it is undefined whether the signal
At the same time, a sampling clock must be selected.
When using an alternate function of the INTPn pin, set the INTNFENn bit to 0.
(n = 14 to 16)
INTNFCn
2. If noise is generated in synchronization with the sampling clock, eliminate the noise by
3. Noise is not eliminated if the pin is used as a normal input port pin.
After reset: 00H
is detected as a valid edge or eliminated as noise. So that the signal is actually detected
as a valid edge, the same signal level must be input for a duration of 3 clocks or more.
attaching a filter to the input pin.
INTNFENn
INTNFENn
INTNFCn2
0
1
7
0
0
0
0
1
1
Other than above
Note
Enables digital noise elimination
INTNFCn1
R/W
6
0
0
0
1
1
0
0
CHAPTER 4 PORT FUNCTIONS
User’s Manual U18279EJ3V0UD
Address: INTNFC14 FFFFF310H, INTNFC15 FFFFF312H,
INTNFCn0
5
0
0
1
0
1
0
1
INTNFC16 FFFFF314H
Setting of digital noise elimination
f
f
f
f
f
f
Setting prohibited
XX
XX
XX
XX
XX
XX
4
0
/4
/16
/64
/128
/256
/512
Sampling clock selection
3
0
INTNFCn2 INTNFCn1 INTNFCn0
2
1
0
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