UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 871

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(4) IIC clock select register 0 (IICCL0)
After reset: 00H
Condition for clearing (CLD0 bit = 0)
• When the SCL pin is at low level
• When the IICE0 bit = 1 → 0 (operation stop)
• Reset
Condition for clearing (DAD0 bit = 0)
• When the SDA pin is at low level
• When the IICE0 bit = 1 → 0 (operation stop)
• Reset
Digital filter can be used only in high-speed mode.
In high-speed mode, the transfer clock does not vary regardless of DFC0 bit set/clear.
The digital filter is used for noise elimination in high-speed mode.
IICCL0
The IICCL0 register is used to set the transfer clock for the I
The IICCL0 register can be read or written in 8-bit or 1-bit units. However, the CLD0 and DAD0 bits are read-
only.
IICOCKS.IICOCKS0 bits (see 17.4 (7) I
Set the IICCL0 register when the IICC0.IICE0 bit = 0.
Reset sets this register to 00H.
Note Bits 4 and 5 are read-only bits.
Remark
SMC0
CLD0
DAD0
DFC0
CL00
0
1
0
1
0
1
0
1
0
1
The SMC0 and CL00 bits are set in combination with the IICX0.CLX0, IICOCKS.IICOCKS1, and
The SCL pin was detected at low level.
The SCL pin was detected at high level.
The SDA pin was detected at low level.
The SDA pin was detected at high level.
Operates in standard mode.
Operates in high-speed mode.
Digital filter off.
Digital filter on.
F
F
F
XX
XX
XX
/44
/86
7
0
: Selection clock
R/W
Note
6
0
Normal mode
Detection of SCL pin level (valid only when IICC0.IICE0 bit = 1)
Address: FFFFFD84H
Detection of SDA pin level (valid only when IICE0 bit = 1)
CLD0
<5>
User’s Manual U18279EJ3V0UD
2
CHAPTER 17 I
C transfer clock setting method).
Communication clock selection
DAD0
Digital filter operation control
<4>
Operation mode switching
Condition for setting (CLD0 bit = 1)
• When the SCL pin is at high level
Condition for setting (DAD0 bit = 1)
• When the SDA pin is at high level
2
SMC0
C BUS
3
F
F
2
XX
XX
C bus.
/24
/24
DFC0
2
High-speed mode
1
0
CL00
0
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