UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 866

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

864
(2) IIC status register 0 (IICS0)
After reset: 00H
Note This bit is also cleared when a bit manipulation instruction is executed for another bit in the IICS0
Condition for clearing (MSTS0 bit = 0)
• When a stop condition is detected
• When the ALD0 bit = 1 (arbitration loss)
• Cleared by the IICC0.LREL0 bit = 1 (exit from
• When the IICC0.IICE0 bit changes from 1 to 0 (operation
• Reset
Condition for clearing (ALD0 bit = 0)
• Automatically cleared after the IICS0 register is read
• When the IICE0 bit changes from 1 to 0 (operation stop)
• Reset
MSTS0
The IICS0 register indicates the status of the I
The IICS0 register is read-only, in 8-bit or 1-bit units.
However, the IICS0 register can only be read when the IICC0.STT0 bit is 1 or during the wait period.
Reset sets this register to 00H.
communications)
stop)
IICS0
ALD0
0
1
0
1
register.
Slave device status or communication standby status
Master device communication status
This status means either that there was no arbitration or that the arbitration result was a “win”.
This status indicates the arbitration result was a “loss”. The MSTS0 bit is cleared to 0.
MSTS0
<7>
R
ALD0
<6>
Address: FFFFFD86H
EXC0
<5>
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
COI0
Detection of arbitration loss
2
<4>
C bus.
Note
Master device status
Condition for setting (MSTS0 bit = 1)
• When a start condition is generated
Condition for setting (ALD0 bit = 1)
• When the arbitration result is a “loss”.
2
TRC0
C BUS
<3>
ACKD0
<2>
STD0
<1>
SPD0
<0>
(1/3)