UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 920

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

17.16.3 Slave operation
(processing requiring a significant change of the operation status, such as stop condition detection during
communication) is necessary.
that the INTIIC interrupt servicing performs only status change processing and that the actual data communication is
performed during the main processing.
transmitting these flags to the main processing instead of the INTIIC signal.
the communication mode flag and ready flag (the processing of the stop condition and start condition is performed by
interrupts, conditions are confirmed by flags).
device stops returning ACK, transfer is end.
918
The following shows the processing procedure of the slave operation.
Basically, the operation of the slave device is event-driven.
The following description assumes that data communication does not support extension codes. Also, it is assumed
Therefore, the following three flags are prepared so that the data transfer processing can be performed by
The following shows the operation of the main processing block during slave operation.
Start I
For transmission, repeat the transmission operation until the master device stops returning ACK. When the master
(1) Communication mode flag
(2) Ready flag
(3) Communication direction flag
This flag indicates the following communication statuses.
Clear mode:
Communication mode: Data communication in progress (valid address detection stop condition detection,
This flag indicates that data communication is enabled. This is the same status as an INTIIC interrupt during
normal data transfer. This flag is set in the interrupt processing block and cleared in the main processing
block. The ready flag for the first data for transmission is not set in the interrupt processing block, so the first
data is transmitted without clearance processing (the address match is regarded as a request for the next
data).
This flag indicates the direction of communication and is the same as the value of the IICS0.TRC0 bit.
2
C and wait for the communication enabled status. When communication is enabled, perform transfer using
I
2
C
Figure 17-18. Software Outline During Slave Operation
Data communication not in progress
ACK from master not detected, address mismatch)
Setting, etc.
INTIIC
User’s Manual U18279EJ3V0UD
CHAPTER 17 I
Interrupt servicing
Setting, etc.
Data
2
C BUS
Therefore, processing by an INTIIC interrupt
Flag
Main processing