UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 180

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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The clock generator is controlled by the following six registers.
• PLL control register (PLLCTL)
• Processor clock control register (PCC)
• Power save control register (PSC)
• Power save mode register (PSMR)
• Oscillation stabilization time select register (OSTS)
• Clock monitor mode register (CLM)
(1) PLL control register (PLLCTL)
Cautions 1. Be sure to set bits 7 to 2 to “0” and set bit 0 to “1”.
Control Registers
The PLLCTL register selects CPU operation clock.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
2. Setting the SELPLL bit to 1 is enabled only when the PLL clock frequency is stabilized. If
PLLCTL
the SELPLL bit is rewritten when the PLL clock frequency is not stabilized (during unlock),
0 is written to the bit. Therefore, be sure to confirm that the PLL mode has been set.
Use the following program for reference.
_loop:
(next instruction)
After reset:
SELPLL
set1
tst1
bz
01H
0
1
0
Clock-through mode
PLL mode
R/W
1, PLLCTL
1, PLLCTL
_loop
0
CHAPTER 5 CLOCK GENERATOR
Address:
User’s Manual U18279EJ3V0UD
0
FFFFF82CH
CPU operation clock selection
0
0
0
SELPLL
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