UPD70F3453GC-8EA-A Renesas Electronics America, UPD70F3453GC-8EA-A Datasheet - Page 979

• Manufacturer Part Number: UPD70F3453GC-8EA-A
• Description: MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: V850E/Ix3r

Specifications of UPD70F3453GC-8EA-A

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Data Converters: A/D 10x12b, 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.5 Transfer Types
19.5.1 2-cycle transfer
(DMAC to destination).
second cycle, the destination address is output and writing is performed from the DMAC to the destination.
19.6 Transfer Target
19.6.1 Transfer type and transfer target
possible”, and the mark “×” means “transfer impossible”.
19.7 DMA Channel Priorities
higher priority DMA transfer request is acknowledged.
In 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle
In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the
Caution An idle cycle of 1 to 2 clocks is always inserted between a read cycle and a write cycle.
Table 19-2 lists the relationship between the transfer type and transfer target. The mark “√” means “transfer
Note If the transfer target is the on-chip peripheral I/O, only the single transfer mode can be used.
Cautions 1. The operation is not guaranteed for combinations of transfer destination and source marked
Remark
The DMA channel priorities are fixed as follows.
In the block transfer mode, the channel used for transfer is never switched.
In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released, the
On-chip
Internal RAM
Internal ROM
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
peripheral I/O
2. Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source and
If DMA transfer is executed to transfer data of an on-chip peripheral I/O register (as a transfer source or
destination), be sure to specify the same transfer size as the register size. For example, to execute
DMA transfer of an 8-bit register, be sure to specify byte (8-bit) transfer.
with “×” in Table 19-2.
destination address of DMA transfer.
Be sure to specify an address between FFFF000H and FFFFFFFH.
Table 19-2. Relationship Between Transfer Type and Transfer Target
Note
CHAPTER 19 DMA FUNCTIONS (DMA CONTROLLER)
Internal ROM
×
×
×
User’s Manual U18279EJ3V0UD
On-Chip Peripheral I/O
Destination
√
√
×
Note
Internal RAM
√
×
×
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