MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 108

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

5
5.8.2
The S2CR1 register provides the control bits that determine word length and select the method
used for the wake-up feature. Bit 5 has an MI BUS control function detailed below (for details of
the other bits see Section 5.6.2).
WOMS2 — Wired-OR mode for SCI pins (PG1, PG0)
MIE2 — Motorola interface bus enable 2
When MIE2 is set, the SCI2 registers, bits and pins assume the functionality required for MI BUS.
5.8.3
The S2CR2 register provides the control bits that enable or disable individual SCI functions. For
details of the bits, see Section 5.6.3.
5.8.4
The bits in S2SR1 indicate certain conditions in the SCI hardware and are automatically cleared
by special acknowledge sequences. For details of the bits, see Section 5.6.4.
MOTOROLA
5-16
SCI2/MI control 1 (S2CR1)
SCI2/MI control 2 (S2CR2)
SCI2/MI status 1 (S2SR1)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
S2CR1 — SCI2 control register 1
S2CR2 — SCI2 control register 2
S2SR1 — SCI2 status register 1
–
–
TXD2 and RXD2 are open drains if operating as inputs.
TXD2 and RXD2 operate normally.
MI BUS is enabled for this subsystem.
The SCI functions normally.
SERIAL COMMUNICATIONS INTERFACE
Address
Address
Address
$0052 LOPS2 WOMS2 MIE2
$0053
$0054 TDRE2
TIE2
bit 7
bit 7
bit 7
TCIE2
bit 6
bit 6
bit 6
TC2 RDRF2 IDLE2
RIE2
bit 5
bit 5
bit 5
ILIE2
bit 4
bit 4
bit 4
M2
WAKE2 ILT2
OR2
bit 3
bit 3
TE2
bit 3
bit 2
bit 2
RE2
bit 2
NF2
RWU2 SBK2 0000 0000
bit 1
PE2
bit 1
bit 1
FE2
MC68HC11PH8
bit 0
PT2
bit 0
bit 0
PF2
0000 0000
1100 0000
on reset
on reset
on reset
State
State
State
TPG