MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 192

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

10
10.2.1
After reset, the CPU fetches the restart vector from the appropriate address during the first three
cycles, and begins executing instructions. The stack pointer and other CPU registers are
indeterminate immediately after reset; however, the X and I interrupt mask bits in the condition
code register (CCR) are set to mask any interrupt requests. Also, the S-bit in the CCR is set to
inhibit the STOP mode.
10.2.2
After reset, the INIT register is initialized to $00, putting the 2K bytes of RAM at locations
$0080–$087F, and the control registers at locations $0000–$007F. The INIT2 register puts
EEPROM at locations $0D00–$0FFF.
10.2.3
When a reset occurs in expanded operating modes, port B, C, and F pins used for parallel I/O are
dedicated to the expansion bus. If a reset occurs during a single chip operating mode, all ports are
configured as general purpose high-impedance inputs.
Note:
10.2.4
During reset, the timer system is initialized to a count of $0000. The prescaler bits are cleared,
and all output compare registers are initialized to $FFFF. All input capture registers are
indeterminate after reset. The output compare 1 mask (OC1M) register is cleared so that
successful OC1 compares do not affect any I/O pins. The other four output compares are
configured so that they do not affect any I/O pins on successful compares. All input capture
edge-detector circuits are configured for capture disabled operation. The timer overflow interrupt
flag and all eight timer function interrupt flags are cleared. All nine timer interrupts are disabled
because their mask bits have been cleared.
The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5; however,
the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin.
MOTOROLA
10-8
Do not confuse pin function with the electrical state of the pin at reset. All
general-purpose I/O pins configured as inputs at reset are in a high-impedance state.
Port data registers reflect the port’s functional state at reset. The pin function is mode
dependent.
Central processing unit
Memory map
Parallel I/O
Timer
RESETS AND INTERRUPTS
MC68HC11PH8
TPG