MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 130

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

7
WCOL — Write collision
Clearing the WCOL bit is accomplished by reading the SPSR (with WCOL set) followed by an
access of SPDR. Refer to Section 7.3.4 and Section 7.4.
MODF — Mode fault
To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to Section
7.3.4 and Section 7.4.
Bits [5, 3:0] — Not implemented; always read zero.
7.5.3
The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this
register initiates transmission or reception of a byte, and this only occurs in the master device. At
the completion of transferring a byte of data, the SPIF status bit is set in both the master and slave
devices.
A read of the SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte
that caused the overrun, the first SPIF must be cleared by the time a second transfer of data from
the shift register to the read buffer is initiated.
SPI is double buffered in and single buffered out.
MOTOROLA
7-8
1 (set)
0 (clear) –
1 (set)
0 (clear) –
SPI data (SPDR)
SPDR — SPI data register
–
–
Write collision.
No write collision.
Mode fault.
No mode fault.
Address
$002A
SERIAL PERIPHERAL INTERFACE
(bit 7)
bit 7
bit 6
(6)
bit 5
(5)
bit 4
(4)
bit 3
(3)
bit 2
(2)
bit 1
(1)
MC68HC11PH8
(bit 0) undeÞned
bit 0
on reset
State
TPG