MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 35
MC68HC711PH8
Manufacturer Part Number
MC68HC711PH8
Description
High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
Manufacturer
Motorola
Datasheet
1.MC68HC711PH8.pdf
(264 pages)
- Current page: 35 of 264
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2.5.4.1
This read/write register contains two bits that are used to enable and disable the synthesizer and
to switch from slow (EXTALi) to one of the fast speeds. Two further bits are used to control the filter
bandwidth. The SCI, timer, timer clock source and the slow clock for WAIT mode are also
controlled by this register.
PLLON — PLL on
This bit activates the synthesizer circuit without connecting it to the control circuit. This allows the
circuit to stabilize before it drives the CPU clocks.
On reset, PLLON is forced low if the VDDSYN supply is low. If VDDSYN is at VDD, PLLON is set
by reset to allow the control loop to stabilize during power-up. PLLON cannot be cleared whilst
using VCOOUT to drive the internal processor clock, i.e. when BCS is set.
BCS — Bus clock select
This bit determines which signal drives the clock circuit generating the bus clocks. Once BCS has
been altered it can take up to [1.5 EXTALi + 1.5 VCOOUT] cycles for the change in the clock to
occur. Reset clears this bit.
Note:
AUTO — Automatic bandwidth control (Test mode only)
Reset sets this bit.
Warning: This bit must be cleared before an attempt is made to use BWC; manual bandwidth
MC68HC11PH8
PLL control (PLLCR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
PLLON and BCS have built-in safeguards so that VCOOUT cannot be selected as the
clock source (BCS = 1) if the PLL is off (PLLON = 0). Similarly, the PLL cannot be
turned off (PLLON = 0) if it is on and in use (BCS = 1). Turning the PLL on and selecting
VCOOUT as the clock source therefore requires two independent writes to PLLCR.
control should always be used.
PLLCR — PLL control register
–
–
–
Switch PLL on.
Switch PLL off.
VCOOUT output drives the clock circuit (4XCLK).
EXTALi drives the clock circuit (4XCLK).
Automatic bandwidth control selected.
Manual bandwidth control selected.
Address
$002E PLLON BCS
bit 7
PIN DESCRIPTIONS
bit 6
AUTO
bit 5
BWC
bit 4
VCOT
bit 3
MCS T16EN WEN x010 1010
bit 2
bit 1
bit 0
MOTOROLA
on reset
State
TPG
2-9
2
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