MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 156

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8
8.1.5.3
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits control the
pulse accumulator and IC4/OC5 functions.
Bits [7, 3] — Not implemented; always read zero
PAEN — Pulse accumulator system enable (refer to Section 8.1.8)
PAMOD — Pulse accumulator mode (refer to Section 8.1.8)
PEDGE — Pulse accumulator edge control (refer to Section 8.1.8)
This bit has different meanings depending on the state of the PAMOD bit.
I4/O5 — Input capture 4/output compare 5 (refer to Section 8.1.8)
RTR[1:0] — RTI interrupt rate select
These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven either by CLK64 or by an ST4XCK/2
of the timer prescaler. These two control bits select an additional division factor. Refer to Table 8-2
and Table 8-3.
MOTOROLA
8-22
Pulse accumulator control (PACTL)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
PACTL — Pulse accumulator control register
–
–
–
Pulse accumulator enabled.
Pulse accumulator disabled.
Gated time accumulation mode.
Event counter mode.
Input capture 4 function is enabled (no OC5).
Output compare 5 function is enabled (no IC4).
Address
$0026
bit 7
0
TIMING SYSTEM
15
PAEN PAMOD PEDGE
bit 6
clock rate that is compensated so it is independent
bit 5
bit 4
bit 3
0
I4/O5
bit 2
RTR1
bit 1
MC68HC11PH8
RTR0 0000 0000
bit 0
on reset
State
TPG