MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 149

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8.1.4.7
Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts.
Note:
OC1I–OC4I — Output compare x interrupt enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.
I4/O5I — Input capture 4/output compare 5 interrupt enable
When I4/O5 in PACTL is set, I4/O5I is the input capture 4 interrupt enable bit.
When I4/O5 in PACTL is zero, I4/O5I is the output compare 5 interrupt enable bit.
IC1I–IC3I — Input capture x interrupt enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.
MC68HC11PH8
Timer interrupt mask 1 (TMSK1)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Ones in TMSK1 enable the
corresponding interrupt sources.
TMSK1 — Timer interrupt mask register 1
–
–
–
OCx interrupt is enabled.
OCx interrupt is disabled.
IC4/OC5 interrupt is enabled.
IC4/OC5 interrupt is disabled.
ICx interrupt is enabled.
ICx interrupt is disabled.
Address
$0022
OC1I
bit 7
TIMING SYSTEM
OC2I
bit 6
OC3I
bit 5
OC4I
bit 4
I4/O5I
bit 3
bit 2
IC1I
bit 1
IC2I
bit 0
IC3I
MOTOROLA
0000 0000
on reset
State
TPG
8-15
8