MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 234

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

12
A.5.2
MOTOROLA
A-10
(1) This mask option does not exist on the MC68HC711PH8, on which the PLL is optimized for use at 32kHz.
(2) Assumes that stable VDDSYN is applied, that an external Þlter capacitor with a value of 47nF is attached to the XFC pin,
(3) Short term stability is the average deviation from programmed frequency measured over a 2 s interval at maximum f
(4) This parameter is periodically sampled rather than 100% tested.
(VDD = 5.0Vdc 10%, VSS = 0Vdc, T
PLL reference frequency
System frequency
PLL output frequency
External clock operation
Capacitor on pin XFC
PLL stabilization time
4XCLK stability
Short term
Long term
and that the crystal oscillator is stable. Stabilization time is measured from power-up to RESET release. This speciÞcation
also applies to the period required for PLL stabilization after changing the X and Y frequency control bits in the
synthesizer control register (SYNR) while PLL is running, and to the period required for the clock to stabilize after WAIT
with WEN = 1.
Long term 4XCLK stability is the average deviation from programmed frequency measured over a 1ms interval at
maximum f
additive to this Þgure.
Characteristic
SYS
PLL control timing
(3)(4)
. Stability is measured with a stable external clock applied Ñ variation in crystal oscillator frequency is
(2)
ELECTRICAL SPECIFICATIONS (STANDARD)
f
Symbol
VCOOUT
C
A
C
t
f
f
f
XTAL
PLLS
REF
SYS
STAB
XFC
= T
L
to T
H
unless otherwise noted)
0.05
TBD
TBD
Min
25
dc
dc
Ñ
Ñ
Mask option 1
Typical
32
47
20
Ñ
Ñ
Ñ
Ñ
Maximum
TBD
TBD
TBD
50
16
16
Ñ
4
TBD
TBD
Min
0.1
50
dc
dc
Ñ
Ñ
Mask option 2
Typical Maximum
614
Ñ
Ñ
47
10
Ñ
Ñ
(1)
2000
TBD
TBD
TBD
MC68HC11PH8
16
16
Ñ
4
Units
MHz
kHz
ms
nF
%
SYS
,
TPG