MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 19

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

Figure
Number
MC68HC11PH8
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
3-3
5-1
5-2
5-3
6-1
6-2
6-3
6-4
7-1
7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
9-1
9-2
9-3
10-1
10-2
10-3
MC68HC11PH8/ MC68HC711PH8 block diagram ..................................................1-3
84-pin PLCC/ CERQUAD pinout .............................................................................2-1
112-pin TQFP pinout ..............................................................................................2-2
External reset circuitry............................................................................................2-3
Oscillator connections (VDDSYN = 0, PLL disabled) .............................................2-4
Oscillator connections (VDDSYN = 1, PLL enabled)..............................................2-5
PLL circuit...............................................................................................................2-6
RAM stand-by connections.....................................................................................2-13
MC68HC11PH8/ MC68HC711PH8 memory map ...................................................3-3
Example of expanded mode FREEZ actions..........................................................3-13
RAM and register overlap.......................................................................................3-15
SCI baud rate generator circuit diagram.................................................................5-1
SCI1 block diagram ................................................................................................5-3
Interrupt source resolution within SCI.....................................................................5-14
MI BUS timing.........................................................................................................6-2
Biphase coding and error detection........................................................................6-3
MI BUS block diagram ............................................................................................6-5
A typical interface between the MC68HC11PH8 and the MI BUS..........................6-6
SPI block diagram...................................................................................................7-2
SPI transfer format..................................................................................................7-3
Timer clock divider chains (PLL enabled — VDDSYN high) ..................................8-5
Timer clock divider chains (PLL disabled — VDDSYN low) ...................................8-6
Capture/compare block diagram.............................................................................8-7
Pulse accumulator block diagram...........................................................................8-24
PWM timer block diagram.......................................................................................8-29
PWM duty cycle......................................................................................................8-34
8-bit modulus timer system.....................................................................................8-36
A/D converter block diagram ..................................................................................9-2
Electrical model of an A/D input pin (in sample mode)...........................................9-3
A/D conversion sequence.......................................................................................9-4
Processing flow out of reset (1 of 2) .....................................................................10-19
Processing flow out of reset (2 of 2) .....................................................................10-20
Interrupt priority resolution (1 of 3) .......................................................................10-21
LIST OF FIGURES
LIST OF FIGURES
Title
MOTOROLA
Number
Page
TPG
xi