MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 64

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

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08/Apr/97@13:55 [DS97 v 4.1]
CME — Clock monitor enable (refer to Section 10)
In order to use both STOP and clock monitor, the CME bit should be set before executing STOP,
then set again after recovering from STOP.
FCME — Force clock monitor enable (refer to Section 10)
When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize
STOP mode, FCME should always be cleared.
CR[1:0] — COP timer rate select bits (refer to Section 10)
These control bits determine a scaling factor for the watchdog timer.
3.3.2.5
LIRDV — LIR driven
This bit allows power savings in expanded modes by turning off the LIR output (it has no meaning
in single chip or bootstrap modes). The LIR pin is driven low to indicate that execution of an
instruction has begun. In order to detect consecutive instructions in a high speed application, this
signal drives high for a quarter of a cycle to prevent false triggering. An external pull-up is required
in expanded modes, while a hardwired VSS connection is possible in single chip modes. LIRDV
is reset to zero in single chip modes, and to one in expanded modes.
CWOM — Port C wired-OR mode (refer to Section 4)
MOTOROLA
3-18
System conÞg. options 2 (OPT2)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
OPT2 — System configuration options register 2
–
–
–
–
Clock monitor enabled.
Clock monitor disabled.
Clock monitor enabled; cannot be disabled until next reset.
Clock monitor follows the state of the CME bit.
Enable LIR push-pull drive.
LIR not driven on MODA/LIR pin.
Port C outputs are open-drain.
Port C operates normally.
OPERATING MODES AND ON-CHIP MEMORY
Address
—this line does not form part of the document—
$0038
LIRDV CWOM STRCH IRVNE LSBF
bit 7
bit 6
bit 5
bit 4
bit 3
SPR2 EXT4X DISE x00x 000t0
bit 2
bit 1
PH8.DS03/Modes+mem
MC68HC11PH8
bit 0
on reset
State
TPG