MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 32

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

2
2.5
The XFC and VDDSYN pins are the inputs for the on-chip PLL (phase-locked loop) circuitry. On reset,
all system clocks are derived from the internal EXTAL signal (EXTALi). If enabled (VDDSYN high), the
PLL uses the EXTALi frequency as a reference to generate a clock frequency that can be varied under
software control. The user may choose to use the PLL output instead of EXTALi as the source clock
for the system.
The PLL consists of a variable bandwidth loop filter, a voltage controlled oscillator (VCO), a
feedback frequency divider and a digital phase detector. PLL functions are controlled by the
PLLCR and SYNR registers. A block diagram of the PLL circuit is shown in Figure 2-6; refer also
to Figure 8-1.
If enabled by the CLK4X bit in the CONFIG register, either the 4XCLK signal or the EXTALi signal
can be output on the 4XOUT pin, depending on the state of the EXT4X bit in the OPT2 register.
Refer to Figure 2-6, and to Section 3 for a description of the CLK4X and EXT4X bits. The signal
output on the 4XOUT pin could be used to clock another MCU.
Note:
MOTOROLA
2-6
XTAL
Key:
EXTAL
The 4XOUT pin is not available on 84-pin packaged devices.
&
External connection
EXTALi
STOP
Phase-locked loop (XFC, VDDSYN, 4XOUT)
f
REF
Frequency divider
f
FB
Phase
SYNR
detect
PCOMP
Figure 2-6 PLL circuit
C
PIN DESCRIPTIONS
XFC
XFC
Loop Þlter
V
DDSYN
VCO
VDDSYN
EXTALi
0.1 F
0.01 F
VCOOUT
Module clock
4XOUT clock
Bus clock
EXT4X
select
select
select
MCS
BCS
MC68HC11PH8
ST4XCK
For SCI
and timer
4XOUT
4XCLK
To clock
generation
circuitry
TPG