MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 202

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

can be eliminated by writing the ADPU bit to zero and halting the RC clock (CSEL cleared). The
SPI system is enabled or disabled by the SPE control bit. The SCI transmitter is enabled or
disabled by the TE bit, and the SCI receiver is enabled or disabled by the RE bit (lowest power
consumption is achieved when RE=TE=0). Power consumption is reduced if all the PWM enable
bits (PWEN[4:1]) are cleared, thereby disabling every PWM channel. Setting the WEN bit in
PLLCR will result in WAIT mode using a slower clock and hence less power (see Section 2.5).
Therefore the power consumption in WAIT is dependent on the particular application.
10.5.2
STOP
Executing the STOP instruction while the S-bit in the CCR is clear places the MCU in the STOP
condition. If the S-bit is set, the STOP opcode is treated as a no-op (NOP). The STOP condition
offers minimum power consumption because all clocks, including the crystal oscillator, are
stopped while in this mode. To exit STOP and resume normal processing, a logic low level must
be applied to one of the external interrupts (IRQ or XIRQ) or to the RESET pin. A keyboard
interrupt on port H or a pending edge-triggered IRQ can also bring the CPU out of STOP.
Because all clocks are stopped in this mode, all internal peripheral functions also stop. The data
in the internal RAM is retained as long as V
power is maintained. The CPU state and I/O pin
DD
levels are static and are unchanged by STOP. Therefore, when an interrupt comes to restart the
system, the MCU resumes processing as if there were no interruption. If reset is used to restart
the system a normal reset sequence results where all I/O pins and functions are also restored to
their initial states.
To use the IRQ pin as a means of recovering from STOP, the I-bit in the CCR must be clear (IRQ
not masked). The XIRQ pin can be used to wake up the MCU from STOP regardless of the state
of the X-bit in the CCR, although the recovery sequence depends on the state of the X-bit. If X is
clear (XIRQ not masked), the MCU starts up, beginning with the stacking sequence leading to
normal service of the XIRQ request. If X is set (XIRQ masked or inhibited), then processing
10
continues with the instruction that immediately follows the STOP instruction, and no XIRQ
interrupt service is requested or pending.
Because the oscillator is stopped in STOP mode, a restart delay may be imposed to allow oscillator
stabilization upon leaving STOP . If the internal oscillator is being used, this delay is required; however,
if a stable external oscillator is being used, the DLY control bit can be used to bypass this start-up delay.
The DLY control bit is set by reset and can be optionally cleared during initialization. If the DLY equal
to zero option is used to avoid start-up delay on recovery from STOP , then reset should not be used as
the means of recovering from STOP , as this causes DLY to be set again by reset, imposing the restart
delay. This same delay also applies to power-on-reset, regardless of the state of the DLY control bit,
but does not apply to a reset while the clocks are running. See Section 3.3.2.4.
TPG
MOTOROLA
RESETS AND INTERRUPTS
MC68HC11PH8
10-18