UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1087

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(8) UF0 EP status 0 register (UF0EPS0)
UF0EPS0
Remark
This register indicates the USB bus status and the presence or absence of register data.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7)
and the current setting of the interface.
It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been
set. If it is necessary to read the status correctly, therefore, separate writing to the UF0FIC0 and UF0FIC1 registers
from reading from the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN registers by at least four USB clocks.
Bit position
5, 4
3, 2
6
n = 1, 2
7
0
IT1
BKOUTn
BKINn
Bit name
IT1
6
BKOUT2 BKOUT1
These bits indicate that data is in the UF0INT1 register (FIFO). By setting the IT1DEND
bit of the UF0DEND register to 1, the status in which data is in the UF0INT1 register can
be created even if data is not written to the register (Null data transmission). As soon as
the IT1DEND bit of the UF0DEND register is set to 1 even when the counter of the
UF0INT1 register is 0, this bit is set to 1 by hardware. It is cleared to 0 after correct
transmission.
These bits indicate that data is in the UF0BOn register (FIFO) connected to the CPU side.
When the FIFO configuring the UF0BOn register is toggled, this bit is automatically set to
1 by hardware. It is automatically cleared to 0 by hardware when reading the UF0BOn
register (FIFO) connected to the CPU side has been completed (counter value = 0). It is
not set to 1 when Null data is received (toggling the FIFO does not take place either).
These bits indicate that data is in the UF0BIn register (FIFO) connected to the CPU side.
By setting the BKInDED bit of the UF0DEND register to 1, the status in which data is in
the UF0BIn register can be created even if data is not written to the register (Null data
transmission). As soon as the BKInDED bit of the UF0DEND register has been set to 1
while the counter of the UF0BIn register is 0, this bit is set to 1 by hardware. It is cleared
to 0 when a toggle operation is performed.
5
1: Data is in the register.
0: No data is in the register (default value).
1: Data is in the register.
0: No data is in the register (default value).
1: Data is in the register.
0: No data is in the register (default value).
4
BKIN2
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
BKIN1
2
Function
EP0W
1
EP0R
0
0020000EH
Address
Page 1087 of 1509
After reset
00H
(1/2)