UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 796

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Operation timing
SIFn pin capture
INTCFnR signal
INTCFnT signal
CFnTSF bit
SCKFn pin
SOFn pin
SIFn pin
(1) Write 00H to the CFnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CFnCTL0 register, and select the transmission/reception mode, MSB first, and
(4) Set the CFnSTR.CFnTSF bit to 1 by writing the transmit data to the CFnTX register, and start
(5) When transmission/reception is started, output the serial clock to the SCKFn pin, output the transmit
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
(7) To continue transmission/reception, write the transmit data to the CFnTX register again after the
(8) When one transmission/reception is completed, the reception completion interrupt request signal
(9) When a new transmit data is written to the CFnTX register before communication completion, the next
(10) Read the CFnRX register.
Remark
timing
f
continuous transfer mode at the same time as enabling the operation of the communication clock
(f
transmission/reception.
data to the SOFn pin in synchronization with the serial clock, and capture the receive data of the SIFn
pin.
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
INTCFnT signal is generated.
(INTCFnR) is generated, and reading of the CFnRX register is enabled.
communication is started following communication completion.
XX
CCLK
/2 or f
(1)
(2)
(3)
).
n = 0 to 4
(4)
XX
/3, and master mode.
(5)
Bit 7
Bit 7
(6)
Bit 6
Bit 6
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
(7)
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
Bit 2
Bit 2
Bit 1
Bit 1
(8) (9) (10) (11)
Bit 0
Bit 0 Bit 7
Bit 7
Bit 6
Bit 6
Bit 5 Bit 4 Bit 3
Bit 5 Bit 4 Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
(12)
Bit 0
Bit 0
(13) (15)
Page 796 of 1509
CCLK
) =
(1/2)