UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 543

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
Note The counter can operate in a range from 0000H to the set value of the TT0CCR0 register.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(5) Controlling bits of TT0CTL2 register
Encoder compare
mode
The setting of the TT0CTL2 register in the encoder compare mode is shown below.
(a) Outline of each bit
Mode
<1> The TT0UDS1 and TT0UDS0 bits identify the counting direction (up or down) of the 16-bit counter by the
<2> The TT0ECM1 and TT0ECM0 bits control clearing of the 16-bit counter when its count value matches the
<3> The TT0LDE bit controls a function to transfer the set value of the TT0CCR0 register to the 16-bit counter
phase input from the encoder input pin (TENC00 or TENC01).
value of the CCR0 or CCR1 buffer register.
when the counter underflows. The TT0LDE bit is valid only when the TT0ECM1 and TT0ECM0 bits are 00
and 01, respectively. It is invalid when these bits are set to any other values.
Can be set to 00,
TT0UDS0 Bits
01, 10, or 11.
TT0UDS1,
(<1>)
Table 9-8. Setting of TT0CTL2 Register
TT0ECM1 Bit
(<2>)
0
1
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
TT0ECM0 Bit
(<2>)
0
1
0
1
TT0LDE Bit
Invalid
Invalid
(<3>)
0
1
0
1
(Target Compare
Counter Clear
TT0CCR0,
TT0CCR0
TT0CCR1
TT0CCR1
Register)
−
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Possible
Transfer to
Possible
Counter
−
−
−
−
Note