UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 590

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(a) Setting procedure
(i) Setting of high-impedance control operation
(ii) Changing setting after enabling high-impedance control operation
(iii) Resuming output when pins are in high-impedance state
(iv) Making pin go into high-impedance state by software
<1> Set the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits.
<2> Set the HZA0DCEn bit to 1 (enable high-impedance control).
<1> Clear the HZA0DCEn bit to 0 (to stop the high-impedance control operation).
<2> Change the setting of the HZA0DCMn, HZA0DCNn, and HZA0DCPn bits.
<3> Set the HZA0DCEn bit to 1 (to enable the high-impedance control operation again).
If the HZA0DCMn bit is 1, set the HZA0DCCn bit to 1 to clear the high-impedance state after the valid
edge of the external pin is detected. However, the high-impedance state cannot be cleared unless this bit
is set while the input level of the external pin is inactive.
<1> Set the HZA0DCCn bit to 1 (command signal to clear the high-impedance state).
<2> Read the HZA0DCFn bit and check the flag status.
<3> Return to <1> if the HZA0DCFn bit is 1. The input level of the external pin must be checked.
The HZA0DCTn bit must be set to 1 by software to make the pin go into a high-impedance state while the
input level of the external pin is inactive. The following procedure is an example in which the setting is not
dependent upon the setting of the HZA0DCMn bit.
<1> Set the HZA0DCTn bit to 1 (high-impedance output command).
<2> Read the HZA0DCFn bit to check the flag status.
<3> Return to <1> if the HZA0DCFn bit is 0. The input level of the external pin must be checked.
However, if the external pin is not used with the HZA0DCPn bit and HZA0DCNn bit cleared to 0, the pin
goes into a high-impedance state when the HZA0DCTn bit is set to 1.
Remark
The pin can function as an output pin if the HZA0DCFn bit is 0.
The pin is in a high-impedance state if the HZA0DCFn bit is 1.
n = 0, 1
CHAPTER 11 MOTOR CONTROL FUNCTION
Page 590 of 1509