UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 250

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
7.5.2
TAAnCTL0.TAAnCE bit is set to 1, and an interrupt request signal (INTTAAnCC0) is generated each time the specified
number of edges have been counted. The TOAAn0 pin cannot be used.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
In the external event count mode, the valid edge of the external event count input is counted when the
Usually, the TAAnCCR1 register is not used in the external event count mode.
TIAAn0 pin
(external event
count input)
INTTAAnCC0 signal
TAAnCCR0 register
External event count mode (TAAnMD2 to TAAnMD0 bits = 001)
16-bit counter
TAAnCE bit
Remark
Remarks 1.
FFFFH
0000H
2.
n = 0 to 3, 5
This figure shows the basic timing when the rising edge is specified as the valid edge
of the external event count input.
n = 0 to 3, 5
detector
External
event
count
interval
(D
Figure 7-14. Configuration in External Event Count Mode
Edge
Figure 7-15. Basic Timing in External Event Count Mode
0
D
+ 1)
0
TAAnCE bit
External
event
count
interval
(D
D
0
D
+ 1)
0
0
External
event
count
interval
(D
0
D
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
+ 1)
0
CCR0 buffer register
TAAnCCR0 register
16-bit counter
INTTAAnCC0 signal
TAAnCCR0 register
(TIAAn0 pin input)
Clear
External event
16-bit counter
Match signal
count input
D
0
− 1
D
INTTAAnCC0 signal
D
0
0
Page 250 of 1509
0000
0001