UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 529

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(c) Processing of overflow when two capture registers are used
Care must be exercised in processing the overflow flag when two capture registers are used. First, an example
of incorrect processing is shown below.
When two capture registers are used, and if the overflow flag is cleared to 0 by one capture register, the other
capture register may not obtain the correct pulse width.
Use software when using two capture registers. An example of how to use software is shown below.
The following problem may occur when two pulse widths are measured in the free-running timer mode.
<1> Read the TT0CCR0 register (setting of the default value of the TIT00 pin input).
<2> Read the TT0CCR1 register (setting of the default value of the TIT01 pin input).
<3> Read the TT0CCR0 register.
<4> Read the TT0CCR1 register.
TT0CCR0 register
TT0CCR1 register
INTTT0OV signal
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
Read the overflow flag. Because the flag is cleared in <3>, 0 is read.
Because the overflow flag is 0, the pulse width can be calculated by (D
TIT00 pin input
TIT01 pin input
16-bit counter
TT0OVF bit
Example of incorrect processing when two capture registers are used
TT0CE bit
FFFFH
0000H
D
00
<1>
D
10
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
<2>
D
00
D
D
01
10
<3>
D
11
<4>
11
D
01
− D
10
D
) (incorrect).
11
01
− D
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00
).