UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1152

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) UF0 EP0 status register L (UF0E0SL)
UF0E0SL
This register stores the value that is to be returned in response to the GET_STATUS Endpoint0 request.
This register can be read or written in 8-bit units. Note, however, that data can be written to this register only when
the EP0NKA bit is set to 1.
If an error occurs in USBF, the E0HALT bit is set to 1 by FW. A write access to this register is ignored while a USB-
side access to Endpoint0 is being received.
When the E0HALT bit is set to 1 by FW, it is not reflected until the next SETUP token is received if the control
transfer immediately before is for the SET_FEATURE Endpoint0, CLEAR_FEATURE Endpoint0, GET_STATUS
Endpoint0 request, or an FW-processed request.
The hardware automatically transmits the contents of this register to the host when it has received the
GET_STATUS Endpoint0 request. If Endpoint0 has stalled, the UF0E0W and UF0E0R registers are cleared, and
the EP0NKW and EP0NKR bits of the UF0E0N register are cleared to 0.
Caution To rewrite this register, set the EP0NKA bit to 1 before reading the register contents, and rewrite
Bit position
0
the register contents after confirming that the bit has been set, in order to prevent conflict
between a read access and a write access.
7
0
E0HALT
Bit name
6
0
This bit indicates the status of Endpoint0.
This bit is set to 1 by hardware when the SET_FEATURE Endpoint0 request has been
received, and cleared to 0 by hardware when the CLEAR_FEATURE Endpoint0 request
has been received. DATA PID is initialized to DATA0.
5
0
1: Stalled
0: Not stalled
4
0
CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
3
0
2
0
Function
1
0
E0HALT
0
0020014CH
Address
Page 1152 of 1509
After reset
00H